1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a device and a fabrication process whereby a Magnetoresistive Random Access Memory (MRAM) structure can be used as a selectively programmable antifuse device.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of binary data. Conventional semiconductor electronic storage devices incorporate capacitor type structures, which are referred to as Dynamic Random Access Memory (DRAM), that temporarily store binary data based on the charged state of a capacitor. This type of semiconductor Random Access Memory (RAM) requires a continuous supply of power and a periodic charge refresh to maintain a particular defined logic-state. As a result, semiconductor RAM is considered volatile memory due to the fact that data can be lost with the loss of power. For many applications, it may be desirable to replace traditional volatile memory with an improved solid-state non-volatile memory device. This need has fueled research and development in the area of non-volatile memory storage devices while still maintaining a high-density fabrication process and technique. The increased demand for a more sophisticated, efficient, and non-volatile data retention technique has driven the development of Magnetoresistive Random Access Memory (MRAM) devices.
MRAM is a developing technology that offers the advantages of non-volatility and high-density fabrication. MRAM structures employ the spin property of electrons within layers of magnetic material to read the memory storage logic states. Binary logic states typically take advantage of a resistance differential to distinguish between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states. Resistance is a measure of the inability of an electrical current to flow through a specific material, whereas current is the actual flow of charge carriers through a material. If a material has a high resistance, then the ability of electrons to flow through the material is inhibited. Conversely, a low resistive material tends to allow a higher degree of current to flow.
MRAM structures take advantage of this resistivity concept by manipulating the alignments of spin states within multiple layers of material to increase or decrease the resistance of a material. Magnetic Tunnel Junctions (MTJ), for example, are electronic structures that exhibit a high resistance across the tunneling dielectric structure. MTJ based MRAM devices incorporate at least two thin layers of magnetic material separated by an insulating tunnel barrier. The magnetic and insulating layers are fabricated on the substrate, The MRAM magnetic layers consist of a magnetic pinned layer and a magnetic sense layer. The selective programmability of the sense layer enables the MRAM structure to act as a logic state device, which stores binary data as directions of net magnetization vectors in the metallic MTJ layers. Current flow through two orthogonal conductive traces induces a magnetic moment in a parallel or anti-parallel configuration between the pinned layer and the sense layer.
MRAM structures employ the nature of spin dependent variable resistance when used to define logic states wherein the high and low resistivity states represent a logical xe2x80x9c1xe2x80x9d, or xe2x80x9c0,xe2x80x9d respectively. The corresponding parallel and antiparallel magnetization states reflect and represent two different resistances. The overall MTJ resistance has minimum and maximum values when the net magnetization vectors of the two individual magnetic layers point in substantially the same (parallel) and opposite (antiparallel) directions, respectively. When these materials are layered in a particular fashion, they exhibit a variable vertical electrical resistance depending on the magnetization state of the individual layers.
Due to the physical arrangements of MTJ layers, MRAM structures may be fabricated using similar integration techniques as conventional DRAM. In addition, integrated circuits often implement permanent programmable electrical connections between circuit nodes. One type of permanent programmable electrical connections is referred to as an antifuse link. Field Programmable Gate Array (FPGA) devices may employ antifuse structures for their high-density fabrication ability and efficient ease of programmability. Application Specific Integrated Circuits (ASICs) may make use of antifuses for effective system logic implementation on a single chip.
A fuse is often used in an electrical circuit to inhibit the excessive flow of electrons by creating a permanent open circuit at the fuse. When a fuse is xe2x80x9cblown,xe2x80x9d the permanently open circuit stops the flow of charge carriers through the electrical circuit at the fuse. In contrast, an antifuse is often used in an electrical circuit to allow an open flow of charge carriers by creating a permanent short circuit at the fuse. When an antifuse is xe2x80x9cblown,xe2x80x9d a permanent short is created at the antifuse.
Conventional antifuse devices in a DRAM array may be fabricated with a structure similar to that of a capacitor, i.e., a dielectric layer separated by two conductive electrical terminals. Initially, an antifuse device is fabricated in the xe2x80x9coffxe2x80x9d state, which presents a high resistance between antifuse terminals. Conversely, the xe2x80x9conxe2x80x9d state represents a lower resistive connection between antifuse terminals. To program an antifuse xe2x80x9conxe2x80x9d state, a large programming voltage, usually between 7 and 9 volts, may be applied across the antifuse terminals, which causes breakdown of the interposed dielectric and forms a short circuit between the antifuse terminals. However, the short circuit produced by high voltage is unreliable. Accordingly, alternative methods, such as laser fusing is generally employed to program antifuses in DRAM circuits. Though more reliable, such processes are cumbersome, particularly where they depend upon the use of different materials on structures from adjacent cell capacitors, which may require additional processing steps during fabrication. An even larger voltage could be used to better break down the dielectric material, but such a voltage is more likely to cause damage to neighboring circuitry.
Hence, the use of conventional antifuse devices in MRAM types of devices may be expensive in terms of production costs and in terms of loss of available space for other circuit components. Additionally, the use of conventional antifuse devices may potentially cause damage to neighboring circuit components due to the relatively high programming voltage needed to change the antifuse from a non-conducting state to a conducting state. Thus, there exists a need for an improved method of manufacturing antifuse devices that do not consume as much substrate space and do not add additional processing steps to the process of fabricating integrated circuitry. More particularly, there is a need for an antifuse device that is better suited for fabrication with MRAM type devices that may be programmed in a safer manner.
The aforementioned needs are satisfied by the present invention which, in one aspect, is comprised of a memory device. The memory device includes a substrate having a first surface and a first plurality of magnetic tunnel junction (MTJ) devices formed on the substrate. The first plurality of MTJ devices are logically interconnected to form a memory array, wherein logical data can be stored by selective magnetization of individual MTJ devices of the array. The memory device further includes at least one antifuse MTJ device formed on the substrate, wherein the antifuse MTJ device is electrically interconnected to the memory device. Selective application of a xe2x80x9chighxe2x80x9d voltage to the antifuse device blows the tunneling dielectric. Advantageously, the process allows for the simultaneous fabrication of antifuse devices along with the fabrication of the MTJ devices forming the memory array.
In another aspect, the present invention comprises an antifuse device for an integrated circuit formed on a substrate. The antifuse device comprises a first layer of magnetic material formed on an exposed surface of the substrate, a second layer of magnetic material positioned on top of the first layer and a dielectric layer interposed between the first layer and the second layer wherein the first layer, the second layer and the dielectric layer form a magnetic tunnel junction device. In this aspect, the device further includes a logic circuit that is selectable so as to interconnect the first layer to a first electrical potential such that the first and second layers of magnetic material are shorted together when the logic circuit is selected. The use of the magnetic layers and the dielectric layer results in an antifuse device that can be shorted at a relatively low voltage, e.g., 1.8 volts.
In yet another aspect, the present invention comprises a method of forming a magnetic random access memory array device comprising simultaneously forming a plurality of first layers of magnetic material on a semiconductor substrate, wherein at least one of the first layers of magnetic material is for an antifuse device. The method further comprises simultaneously forming a plurality of dielectric layers on the plurality of first layers of magnetic material wherein at least one of the dielectric layers is for the antifuse device and also simultaneously forming a plurality of second layers of magnetic material on the plurality of dielectric layers wherein at least one of the second layers of magnetic material is for the antifuse device. The method further comprises electrically interconnecting the antifuse device to a source of electrical potential such that application of the electrical potential results in the antifuse device being shorted.
These and other objects and advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.